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A three-bit dynamic latch contains 3 non-inverting dynamic latch cells made by using the ECIF buildings block at mask level within Chipwise. So I will start by building the one-bit latch…
One-Bit Latch
The output graph should look a little like this…
So If I recreate this circuit as a STX diagram in Chipwise I get the following…
So I check for errors and if all clear I can proceed to generate my ECIF diagram…
With the ECIF diagram generated I need to extract and run DRC to test for any errors.
To simulate I need to create an input pulse along with four clock pulses (two clocks and then the NOT clock of each)...
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